An Improved High-Resolution DPWM Control Circuit Based on FPGA

Delay-Line Sharing Based: A New 600-MHz 16-bit Resolution CMOS DPWM Circuit

This paper presents a new circuit design for digital pulse-width modulators (DPWM). In this paper, we improve the structure of hybrid DPWM by utilization of the separation of MSB/LSB group. In addition, a delay line element is shared by MSB/LSB group to reduce the power consumption. The new DPWM prototype circuit operates at 600 MHz clock frequency and has 1.1-mW power consumption. An experimen...

High Speed DPWM Switched Mode Supply and Control

An Efficient LUT Design on FPGA for Memory-Based Multiplication

An efficient Lookup Table (LUT) design for memory-based multiplier is proposed.  This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage ...

An Improved Control Method Based on Modified Delta-Sigma Modulator for Buck Converter

This paper proposes an improved control method based on modified Delta-Sigma Modulator (DSM) to enhance transient response and improve harmonic contents of buck DC-DC converter. The main advantages of the proposed method are improving the output voltage frequency spectrum, correction of the output voltage harmonic contents and sideband harmonics, reduction of switching noise peaks at the output...

Fpga-based Chirp Generator for High Resolution Uav Sar

This paper discusses the design and development of a FPGA-based chirp generator for high resolution Unmanned Aerial Vehicle (UAV) Synthetic Aperture Radar. The desired bandwidth of the chirp signal is 100MHz (combination of I and Q channels) with a chirp rate of 5MHz/μs. Two algorithms based on the Memory-based architecture and the Direct Digital Synthesizer (DDS) architecture are presented. Th...